1. Field of the Invention
The present invention relates to a layout method and a layout apparatus for a semiconductor integrated circuit, and more particularly, to a layout method, and a layout apparatus for a semiconductor integrated circuit for performing cell-based layout of a semiconductor integrated circuit by using library data.
2. Description of Related Art
A cell-based IC (Integrated Circuit) is suitably used for an LSI such as an ASIC (Application Specific Integrated Circuit), an ASSP (Application Specific Standard Product) and a microprocessor, in which high integration and high performance are requested. The cell-based IC is manufactured by combining cells provided by a semiconductor maker and individual circuits designed by the user. Various types and size of cell patterns are provided in the cell library and include a primitive cell pattern in which a pattern for a basic circuit is provided and a macro cell in which a pattern for a circuit such as a CPU and a memory is provided. Since such cells are arranged and wired on an area for a semiconductor chip by using an arrangement & wiring tool, design time and design cost can be reduced. Also, since a layout of CPU or the like can be incorporated as a macro cell, a system LSI can be easily designed.
However, with reduction in a wiring width in the LSI, variation in a gate size due to an optical proximity effect and variation in an amount of etching causes a problem. When a gate density varies depending on location in a gate peripheral area, a gate pattern varies in shape depending on location due to the optical proximity effect. Also, since a degree of penetration of etchant varies depending on the pattern density, a variation in gate size and gate shape after etching is caused at locations of different gate densities. Variation in characteristics of a transistor due to variation in gate size degrades product performance and contributes to a decrease in yields. For this reason, generally in a layout design phase, OPC (Optical Proximity Correction) processing is performed to correct a mask pattern in consideration of the optical proximity effect. A correction pattern is added or gate size is corrected, in the OPC processing, in consideration of the variation in gate size due to the optical proximity effect.
As the wiring width in LSI is further decreased, OPC processing with higher accuracy has been required. For this reason, an amount of calculation and thus calculation time of the OPC processing have increased.
A technique for solving such problems is described in, for example, Japanese Patent Application Publication (JP-P2004-288685A). In this example, a layout designing method for a semiconductor integrated circuit includes a step of arranging a dummy polysilicon fill cell adjacent to a boundary of a basic cell arrangement inhibition area. Thus, the basic cell or the dummy polysilicon fill cell is necessarily arranged in an area adjacent to the basic cell pattern. As a result, a distance between a gate pattern in the basic cell pattern and a gate pattern (or polysilicon interconnection pattern) in another cell (including a dummy polysilicon fill cell) falls within a certain range. Thereby, variation of the gate due to the optical proximity effect and an etching can be suppressed.
According to a conventional technique, the dummy polysilicon fill cell for suppressing an optical proximity effect is arranged to be adjacent to a basic cell located in a direction perpendicular to a gate channel direction (column direction). For this reason, cells are laid out so that a distance between a gate pattern in the basic cell and a polysilicon gate pattern in the cell adjacent to the basic cell in a column direction falls within a certain range.
However, according to the method described in Japanese Patent Application Publication (JP-P2004-288685A), a distance between the gate pattern in the basic cell and the gate pattern in the cell pattern adjacent to the basic cell pattern in a row direction is not considered. For this reason, in a vicinity of boundary of the adjacent different cell lines, a distance between the gate patterns and a data density (gate area density in consideration of a gate length, a gate width and the number of gates) may represent different values. Hereinafter, this conventional technique will be described with reference to FIG. 1.
FIG. 1 is a plan view showing a layout of the semiconductor chip on which cells are arranged according to a method of conventional technique. Here, it is assumed that a plurality of cell patterns 100 are aligned in a row Li on a pattern of a semiconductor chip 1, and cell patterns 110, 120 and 130 are aligned in an adjacent row Li-1. Here, a direction of the gate pattern width is defined as a column direction (Y direction) and a direction perpendicular to the gate width is defined as row direction (X direction).
Generally, cells are arranged in consideration of area costs and wiring. However, a gate data density in a vicinity of a boundary of adjacent cells in the Y direction is not considered. For this reason, even in the boundary of adjacent cell patterns in the Y direction, areas of higher data density and lower data density appear depending on location. For example, referring to FIG. 1, with respect to gate patterns in the cell patterns 100 in the row Li adjacent to the row Li-1, data densities of the gate patterns in peripheral areas are compared with each other. Here, a periphery of the gate pattern in the cell pattern 100 adjacent to the cell pattern 110 is defined as an area A0, a periphery of the gate pattern in the cell pattern 100 adjacent to the cell pattern 120 is defined as an area B0 and the periphery of the gate pattern in the cell pattern 100 adjacent to the cell pattern 130 is defined as an area C0. Given that the data density of the gate pattern in the area B0 is a reference density, since a gate distribution in the cell patterns in the column direction (Y direction) is not considered, data densities in the area AO and the area C0 may be different from the reference density. Here, the data density in the area A0 is higher than the reference density and the data density in the area C0 is lower than the reference density.
As described above, when layout is performed without considering the gate densities in the vicinity of the boundary of the adjacent cells in the column direction (Y direction), the data densities in the gate peripheral areas provided in the vicinity of the boundary may become ununiform. In this case, the shape of gate pattern varies due to the optical proximity effect, depending on a different gate density. Since the amount of etching varies depending on gate density, gate size and gate shape vary depending on the different gate density. For this reason, according to the layout method of the conventional technique, driving characteristics of a transistor provided in the vicinity of the boundary of adjacent cells in the column direction are within a variation, deteriorating product performance.